Flip-chip semiconductor devices continue to gain popularity in the semiconductor industry due to the reduced size or footprint of the device upon being mounted to a user's substrate. In flip-chip devices, a semiconductor die is flip-chip mounted (active side down) to the user substrate, and electrical connections are made between the user's substrate and the active circuitry of the die through a plurality of conductive bumps. Typically, the conductive bumps are pre-formed on the active surface of the semiconductor die. The conductive bumps can be made of solder, gold, a conductive epoxy, or the like, and can be formed by selective evaporation, plating, or using a lithographic patterning process.
Regardless of the bump material or the manner in which the bumps are formed, conductive bumps formed on the die have a tendency to become deformed prior to the time the user is ready to flip-chip mount the die to a substrate. A primary cause of bump deformation is that induced by testing the die. Testing the die, be it in the form of probe, functional test, or burn-in, involves physically contacting the conductive bumps of the die with some form of test contact, such as a probe needle, an array probe wire, a test pin, or the like. If the bump material is soft (e.g. in the case of gold or lead-tin solder bumps), deformation is more likely. Likewise, if testing is performed at an elevated temperature (e.g. above 70.degree. C.) or for extended periods of time (e.g. over several hours), deformation is more likely.
Examples of problems associated with deformed bumps include the following: if deformed too badly 1) a bump can electrically short-circuit to a neighboring bump; 2) it can be difficult to connect the bump through a solder mask opening on the user's substrate; 3) it can be difficult to make adequate contact to a pad on the user's substrate; 4) a vision system can reject the bump as defective or may not be able to recognize the bump; 5) the deformation can lead to the creation of voids in the bump; 6) there may be insufficient standoff height between the die and the user substrate once attached; and 7) the mere appearance of the bump will cause the die to be rejected by the customer or user.
Prior art solutions to overcome the problems associated with deformed bumps are not cost-effective solutions. One solution is to expose the die to an elevated temperature reflow operation. For example, if using a high-lead solder (e.g. greater than 90% lead and less than 10% tin), a reflow at or above 300.degree. C. (e.g. at 365.degree. C.) will cause the solder to melt and reform in an essentially spherical shape, without evidence of the prior deformation. However, such a reflow process is time consuming and requires a flux material to be applied and removed from the die. If performed at the die level, as opposed to the wafer level, the application and removal of the flux material is quite cumbersome. Furthermore, such a reflow process cannot be used with conductive solder bumps where the lead and tin (or other bump constituents) are not commingled, such as in the case of forming an Extended Evaporated Eutectic (E-3) bump as taught in U.S. Pat. No. 5,470,787 by Greer et al. and assigned to the assignee hereof.
Accordingly, there is a need in the semiconductor industry for a method for testing bumped semiconductor devices without excessively deforming or otherwise damaging the bumps. Furthermore, it is desirable that such a method be cost-effective, be performed with minimal or no additional processing steps, and be extendible as bump dimensions shrink.